略歴
学歴・取得学位
山口大学 文理学部 理学科 卒業〔理学士〕
神戸大学大学院 理学研究科 物理学専攻 修士課程 修了〔理学修士〕
神戸大学大学院 自然科学研究科 物理学専攻 博士後期課程 退学
大阪大学大学院 工学研究科 電子工学専攻 博士後期課程 修了
「スタンダードセルLSIの配置配線手法に関する研究」により、大阪大学より博士（工学）の学位を授与される。
主な職歴
松下電器産業株式会社入社 松下電子工業株式会社出向
松下電器産業株式会社 半導体研究センター転属
半導体産業研究所（Semiconductor Industry Research Institute Japan）出向
高知大学 理学部 数理情報科学科 教授
高知大学 教育研究部 自然科学系理学部門 教授
高知大学 教育研究部 自然科学系理工学部門 教授
大阪学院大学 情報学部 教授
所属学会
電子情報通信学会
情報処理学会
IEEE
研究課題
LSI自動設計，最適化アルゴリズム，ビッグデータ分析，画像認識AIモデル
主な研究業績（著書・論文等）
| ｢強磁性イジング薄膜のくりこみ変換｣ | 物性研究, Vol34, No.4, pp.287-296 | 1980.07 |
|---|---|---|
| "Critical behavior of ising magnets: infinitesimal Migdal-Kadanoff approximation," | Journal of physics, C, Solid State Phys., 14, No19, July 1981, L545-L549 O.Nagai, M.Toyonga | 1981.07 |
| "Effects of bond disordered in the ising spin glass problem," | Journal of Magnetism and Magnetic Materials 31-34, pp.1313-1314, 1983 O.Nagai, M.Toyonaga, Diefp-The-Hung, | 1983.02 |
| "Exact calculation for a three-dimensional classical heisenberg magnet," | International Conference on Magnetism, 1985 Y.Miyatake, M.Toyonaga, M.Yamamoto, O.Nagai, | 1985.08 |
| "Phase transition of a three-dimensional quantum heisenberg magnet: Monte Carlo simulations," | International Conference on Magnetism, 1985 Y.Miyatake, M.Toyonaga, K.Nishio, Y.Yamada, O.Nagai, | 1985.08 |
| "Monte carlo studies for three-dimensional quantum-spin models," | Journal of Magnetism and Magnetic Materials 54-57, 1986 Y.Myatake, Y.Yamada, K.Nishino, O.Nagai, M.Toyonaga, | 1986.02 |
| "On the implementation of the heat bath algorithm for Monte-Carlo simulations of classical Heisenberg spin systems," | Journal of physics, C, Solid State Phys., 19, 1986 Y.Myatake, M.Yamada, JJ.Kim, O.Nagai, M.Toyonaga, | 1986.03 |
| "A placement optimization by trembling-spot check," | Transaction of ICICE, Vol.E 72, No.12, p.1350-1359, 1989 Masahiko Toyonaga, Hiroaki Okude, Toshiro Akino, | 1989.10 |
| "Placement optimization by trembling-spot check," | Technical Digest of 1989 Internaltional Conference on VLSI and CAD, Oct 1989, pp85-88 Masahiko Toyonaga, Hiroaki Okude, Toshiro Akino, | 1989.10 |
| "A Topological Channel Router and Channel Compaction," | Proceedings of SASIMI 1990, pp308-315 Yoshiyuki Kawakami, Koichi Satoh, Masahiko Toyonaga, Toshiro Akino, | 1990.10 |
| "Circuit Partitioning by Trembling Spot-Check," | IFIP Workshop on Design & Test of ASIC, 1990, pp45-47 Masahiko Toyonaga, Hiroaki Okude, Toshiro Akino, | 1990.10 |
| "Placement and global wiring optimization by trembling spot-check," | Proceedings of SASIMI 1990,pp300-307 Masahiko Toyonaga, Hiroaki Okude, Toshiro Akino, | 1990.10 |
| 『VLSI Logic Syntehsis and Design』 | オーム社（ISBN4‐274‐03312‐0）豊永昌彦、奥出博昭、秋濃俊郎他 | 1991 |
| "A pin assignment and global routing algorithm for floor-planning," | Proc. of SASIMI 1992, pp424-433 Takahiro Shiohara, Atsushi Yamamoto, Masahiko Toyonaga, Toshiro Akino, | 1992.04 |
| "STANZA：channel routing based on the vertical constraints global minimization," | Proceedings of the 5-th Karuizawa Workshod on Circuit and Systems, pp.381-386, 1992 岩崎知恵, 豊永昌彦, 秋濃俊郎, | 1992.04 |
| "A new approach of fractal dimension based module clustering for VLSI layout," | Proceedings of International Symposium on Circuit and System(ISCAS) 94, pp185-188 Masahiko Toyonaga, Shih-Tsung Yang, Toshiro Akino, Isao Shirakawa, | 1994.05 |
| "A multi-layer channel router using simulated annealing," | Transaction of IEICE, Vol.E 77-A, No.12, December, 1994, pp.2085-2091 Masahiko Toyonaga, Chie Iwasaki, Yoshiaki Sawada, Toshiro Akino, | 1994.12 |
| " A new approach of fractal-analysis based module clustering for VLSI layout, " | Transaction of IEICE, Vol.E 77-A, No.12, December, 1994, pp.2045-2052 Masahiko Toyonaga, Shih-Tsung Yang, Isao Shirakawa, Toshiro Akino, | 1994.12 |
| 「レイアウト配線長推定に基づく最適論理合成の一手法」 | Proceedings of the 11-th Work-shop on Circuit and Systems in Karuizawa, 1998 高橋美和夏, 世古佳弘, 福本美奈子, 木村文浩, 豊永昌彦 | 1998.04 |
| 「シミュレーテドフェーズトランジション法による配置最適化手法」 | Proceedings of the 12-th Work-shop on Circuit and Systems in Karuizawa, pp451-456, 1999 黒川圭一, 石橋典子, 豊永昌彦 | 1999.04 |
| 「動的クロックタイミング割り当てによる準同期クロック合成」 | 情報処理学会 DAシンポジウム2000 論文集, Vol.2000,No.8, pp.43-48 安井卓也，黒川圭一，豊永昌彦,高橋篤司 | 2000.07 |
| "WSSA:A high performance simulated annealing and its application to transistor placement," | Transaction of IEICE, Vol.E 83-A, No.12, December, 2000, pp.2584-2591 Shunji Saika, Masahiro Fukui, Masahiko Toyonaga, Toshiro Akino, | 2000.12 |
| "A Practical Clock Tree Synthesis for Semi-Synchronous Circuits," | Transaction of IEICE, Vol.E84-A No.11 pp.2705-2713 2001 Keiichi Kurokawa, Takuya Yasui, Masahiko Toyonaga, Atsushi Takahasi, | 2001.11 |
| 「クロックタイミング余裕度を考慮した遅延修正による回路最適化手法」 | 情報処理学会 DAシンポジウム2002論文集, Vol.2002, No.10, pp.259-264 安井 卓也, 黒川 圭一, 豊永 昌彦, 高橋 篤司 | 2002.07 |
| " A High-Speed and Low-Power Clock Tree Synthesis by Dynamic Clock Scheduling," | IEICE Transaction on Fund., Vol.E85-A,No.12, pp.2746-2755, Dec 2002 Keiichi Kurokawa, Takuya Yasui, Yoichi Matsumura, Masahiko Toyonaga, Atsushi Takahashi, | 2002.12 |
| "Cell Placement Optimization using Phase Transition and Annealing by a Metropolis's Monte-Carlo Simulation," | Proceedings of SASIMI (Workshop on Syntehsis And System Integration of Mixed Information Technologies)2003, pp95-101,April 2003 Masahiko Toyonaga, Keiichi Kurokawa, Toshiro Akino, Shigeo Kuninobu | 2003.04 |
| 「再レイアウトに向けた単純多層迷路配線の有効性の考察」 | 情報処理学会 DAシンポジウム2004論文集, Vol.2004, No.8, pp.115-120,Jul,2004. 豊永昌彦, 武永秀，國信茂郎 | 2004.07 |
| 「ネット配線長を保証するスタンダードセル配置再手法」 | 情報処理学会 DAシンポジウム2004論文集, Vol.2004, No.8, pp.109-114,Jul,2004 豊永昌彦, 山崎雅史，黒川圭一，國信茂郎 | 2004.07 |
| "A Post Layout Watermarking Method for IP Protection," | 2005 IEEE International Symposium on Circuit and Systems(ISCAS) Proceedings, pp6206-6209(May, 2005) Tingyuan Nie, Tomoo Kisaka, Masahiko Toyonaga | 2005.05 |
| "A Watermarking System for IP Protection by a Post Layout Incremental Router," | 42nd Design Automation Conference, pp.218-221(June, 2005) Tingyuan Nie, Tomoo Kisaka, Masahiko Toyonaga, | 2005.06 |
| "A Certain SA Solver TOSA for Global Placement," | Proc. of IEEE Asia Pacific Conference on Circuit and System (APCCAS 2006), pp.485-488(Dec., 2006) DongQing Wang, Masahiko Toyonaga | 2006.12 |
| An Efficient and Reliable Watermarking System for IP Protection, | IEICE Trans. Fundamentals E90-A, No.9, pp.1932-1939（Sep. 2007） | 2007.09 |
| "New Strategy for Doubling-Free Short Addition-Subtraction Chain," | Applied Matematics & Information Sciences - An International Journal, Vol2, No.2,pp123-133. May 2008. Raveen Ravinesh Goundar, Ken-ichi Shiota, Masahiko Toyonaga, | 2008.05 |
| "SPA Resistant Scalar Multiplication using Golden Ratio Addition Chain Method," | IAENG International Journal of Applied Mathematics, vol. 38, issue 2, pp. 83-88, Jun. 2008 Raveen Ravinesh Goundar, Ken-ichi Shiota, Masahiko Toyonaga, | 2008.06 |
| 「クロストークを回避する配置評価の検討」 | 情報処理学会 DAシンポジウム2008論文集, Vol.2008, No.7, pp.61-66,Aug.,2008. 吉田佑馬, 豊永昌彦, 村岡道明 | 2008.08 |
| 「ダイナミック動作を考慮したクロストーク解析手法」 | 情報処理学会 DAシンポジウム2008論文集, Vol.2008, No.7, pp.127-132,Aug.,2008 小林政幸, 豊永昌彦, 村岡道明 | 2008.08 |
| AKEBONO: A Novel Quick Incremental Placer, | International Conference on IC Design and Technology (ICICDT09),pp51-53, May 2009 Xin Zhang, Tsuyoshi Takeuchi, and Masahiko Toyonaga | 2009.05 |
| "Cell Merge: A Basic-Pre-Clustering Clustering Algorithm for Placement," | International Conference on IC Design and Technology (ICICDT09),pp47-50, May 2009. Xin Zhang, Tsuyoshi Takeuchi, and Masahiko Toyonaga, | 2009.05 |
| "XIN:Fast Wirelength Estimation Algorithm for Placement in VLSI Design," | ISDLT09, pp.61-64, May 2009 Xin Zhang, Yuma Yoshida, and Masahiko Toyonaga. | 2009.05 |
| 「レイアウト配置ECOの有効性判定法」 | 情報処理学会 DAシンポジウム2009論文集, Vol.2009, pp.67-72 宮城悠，吉田佑馬，村岡道明，豊永昌彦 | 2009.08 |
| "A Novel Method for Elliptic Curve Multi-Scalar Multiplication," | International Journal of Applied Mathematics and Computer Sciences, vol. 4, no.9, pp. 1-5, 2009. Raveen R. Goundar, Ken-ichi Shiota, and Masahiko Toyonaga, | 2009.09 |
| "Performance Evaluation for Watermarking Techniques," | ICBECS(International Conf. on Biomedical Eng. and Computer Science) 2010, pp.548-551, April, 2010 Tingyuan Nie, Yansheng Li, Xiaoke Xu, Masahiko Toyonaga | 2010.04 |
| 「確率論的配置手法によるパッケージ配線手法の一手法」 | 情報処理学会 DAシンポジウム2010論文集, Vol.2010, No.7, pp.21-26 寺田翔太，宮城悠，村岡道明，豊永 昌彦 | 2010.09 |
| 「高知大学総合情報システムの監視と利用者動向」 | 学術情報処理研究No.14, pp.64-71, Sep. 2010 佐々木正人,斎藤卓也,石黒克也,豊永昌彦 | 2010.09 |
| 「GPGPUを用いた迷路配線実装の一手法」 | 情報処理学会 DAシンポジウム2011論文集, Vol.2011, No.8, pp.147-152 中井駿介，藤井良弥，寺田翔太，村岡道明，豊永 昌彦 | 2011.08 |
| 「領域制約によるクロストークフリー迷路配線法」 | 情報処理学会 DAシンポジウム2012論文集, Vol.2012, No.5, pp.181-186(2012) 藤井良弥，中井駿介，村岡道明，豊永昌彦 | 2012.08 |
| 「GP-GPUを用いた並列論理シミュレーションアルゴリズムの評価」 | 情報処理学会 DAシンポジウム2012論文集, Vol.2012, No.5, pp.109-114(2012) 大菊祥子，橋口拓哉，豊永昌彦,村岡道明 | 2012.08 |
| "A Multilevel Fingerprinting Method for FPGA IP Protection," | Proc. of ISCAS2013, pp.1789-1792(May, 2013) Tingyuan Nie, Yansheng Li Lijian Zhou, Masahiko Toyonaga | 2013.05 |
| "A Multilayer Crosstalk Avoidance Router using Restricted Maze Grids," | Proc. of MWSCAS 2013, pp.641-644(Aug, 2013) Yoshiya Fujii,Michiaki Muraoka,Masahiko Toyonaga, | 2013.08 |
| "A Critical Net Reshape-Router for High-Performance VLSI Layout Design," | Proc. of IEEE Asia Pacific Conference on Circuit and System（APCCAS2014), pp. 587-590(Nov.,2014) Yusuke Morimoto, Mitsuru Matsushita, Michiaki Muraoka, Masahiko Toyonaga, | 2014.11 |
| "YAPSIM: Yet Another Parallel Logic Simulation Using GP-GPU, " | Proc. of SASIMI2015, the 19th Workshop on Synthesis And System Integration of Mixed Information Technologies, pp. 183-186 (March.,2015,Taiwan) Takuya Hashiguchi, Yuichiro Mori, Masahiko Toyonaga, Michiaki Muraoka, | 2015.03 |
| "A Guided Maze-based Length Controllable Router for Signal Delay Matching," | ASP-DAC2017, Student Research Forum, Poster(Jan, 2017) Mitsuru Matsushita, Yuichiro Mori, Masahiko Toyonaga, | 2017.01 |
| 「個人情報のない個人情報のないビッグデータ再生成法とその検証」 | Scientific and Educational Reports of the Faculty of Science and Technology, Kochi University Vol. 1 (2018), No. 5 筒井真璃菜，三戸理誠，江口大介，豊永昌彦 | 2018.03 |
| A Data Re-construction Method for The Big-data Analysis | The Ninth IEEE International Conference on Awareness Science and Technology (iCAST 2018) | 2018.09 |
| "A Single Filter CNN Performance for Basic Shape Classification," | The Ninth IEEE International Conference on Awareness Science and Technology (iCAST 2018), pp139-143 (Sep.19-21, Kyushu-Univ. 2018) Kenya Murata, Masataka Mito, Daisuke Eguchi, Yuichiro Mori, Masahiko Toyonaga, | 2018.09 |
| "Data-Glove for Japanese Sign Language Training System with Gyro-Sensor," | 2018 Joint 10th International Conference on Soft Computing and Intelligent Systems and 19th International Symposium on Advanced Intelligent Systems, pp.1366-1369(Dec.5-8,2018) Yuichiro Mori, Masahiko Toyonaga, | 2018.12 |
| "Facial Expression Sequence Recognition for a Japanese Sign Language Training System," | 2018 Joint 10th International Conference on Soft Computing and Intelligent Systems and 19th International Symposium on Advanced Intelligent Systems, pp.1360-1365(Dec.5-8,2018) Keisuke Yabunaka, Yuichiro Mori, Masahiko Toyonaga, | 2018.12 |
| "A Practical Clock Tree Synthesis for Semi-Synchronous Circuits," | Proceedings of International Symposium on Physical Desing, pp.159-164, 2000 Masahiko Toyonaga, Keiichi Kurokawa, Takuya Yasui, Atsushi Takahasi, | 2020.04 |
| "A Tiny Neural Network Model for Estimating Next 24 Hour Temperature Transition," | The International Conference on System Science and Engineering 2020(ICSSE2020), pp.274-279(Aug31-Sep3,2020). Huidong TANG，Yuichiro MORI，Masahiko TOYONAGA | 2020.08 |
| A Method for Evaluating the Accuracy of Neural Network Estimation Using Attractor Behavior | World Congress on Sustainable Technologies(WCST2020) | 2020.12 |
| "Using Attractor Behavior to Evaluate Neural Network Temperature Accuracy in World Cities," | International Journal of Intelligent Computing Research (IJICR), Volume 12, Issue 1, ISSN: 2042 4655 (Online), pp.1708-1086, March, 2021, Huidong Tang, Yuichiro Mori, Masahiko Toyonaga | 2021.03 |
主な社会的活動等
ASP-DAC98 Program Committee 1999-1998
電子情報通信学会VLD設計技術専門委員会委員1997-1999，2005-2010
第11回 回路とシステム（軽井沢）ワークショップ実行委員会幹事 1998-1999
ASP-DAC2000 Tutorial Vice-Chair 1999-2000
ASP-DAC2004 Technical-Session Vice-Chair 2003-2004
電子情報通信学会 査読委員 2005-現在に至る
電子情報通信学会英論文誌A 編集委員 2005-2006
情報処理学会四国支部 役員 2007-2010
電子情報通信学会四国支部 役員 2012-2013
電気系学会四国支部連合大会 座長 2005,2008,2012,2018,2019,2020,2021
World Congress on Sustainable Technologies(WCST2020) Chairman 2020
講義など協力可能なテーマ
高度情報化社会の動向，半導体産業の動向，計算機の歴史など