教員紹介

略歴

所属学会

電子情報通信学会
情報処理学会
IEEE
ACM

研究課題

集積回路の低消費電力化・高信頼化・製造容易化設計技術

主な研究業績（著書・論文等）

『VLSI Design and Test for Systems Dependability』「Overview of Device Variation」「Monitoring and Compensation for Variations in Device Characteristics」	Springer	2019.1
『Dependable Embedded Systems』「Monitor Circuits for Cross-Layer Resiliency」	Springer	2021.1
「High-Efficiency Light Modulator Using Guided-to-Radiation Mode Coupling: A Proposal,」	Applied Optics, Vol. 20, No. 14, pp. 2439-2443, Masamitsu Nakajima, Hidetoshi Onodera, Ikuo Awai, and Jun-ichi Ikenoue,	1981.7
「Coupled Multimode Analysis of Anisotropic Heterostructure Waveguides and its Application to a Light Modulator,」	Radio Science, Vol. 17, No. 1, pp. 117-124, Masamitsu Nakajima, Hidetoshi Onodera, and Jun-ichi Ikenoue,	1982.1
「Analysis of Graded-Index Fibers by Means of the Transverse Resonance Method,」	Journal of Optical Society of America, Vol. 72, No. 11, pp. 1502-1505, Naoki Shibanuma, Hidetoshi Onodera, Ikuo Awai, Masamitsu Nakajima, and Jun-ichi Ikenoue,	1982.11
「Refractive-Index Measurement of Bulk Materials: Prism Coupling Method,」	Applied Optics, Vol. 22, No. 8, pp. 1194-1197, Hidetoshi Onodera, Ikuo Awai, and Jun-ichi Ikenoue,	1983.4
「Measuring Method of Loss for Optical Waveguides by Use of a Rectangular Glass Probe,」	Mem. Fac. Eng. Kyoto Univ., Vol. 46, No. 4, pp. 24-41, Ikuo Awai, Hidetoshi Onodera, Masamitsu Nakajima, and Jun-ichi Ikenoue,	1984.10
「Light Intensity Modulation Based on Guided-to-Radiation Mode Coupling in Heterostructure Waveguides,」	Applied Optics, Vol. 23, No. 1, pp. 118-123, Hidetoshi Onodera, Ikuo Awai, Masamitsu Nakajima, and Jun-ichi Ikenoue,	1984.1
「High-Efficiency Light Modulator Using Guided-to-Radiation Mode Coupling in a Graded-Index Waveguide,」	Applied Optics, Vol. 25, No. 13, pp. 2175-2183, Hidetoshi Onodera and Masamitsu Nakajima,	1986.7
「循環型スイッチトキャパシタ A-D, D-A 変換器,」	電子通信学会論文誌, Vol. J69-C, No. 10, pp. 1359-1366, 小野寺秀俊，立石哲夫，田丸啓吉,	1986.10
「LSI デザインルールチェック専用計算機のシステム設計,」	電子通信学会論文誌 , Vol. J69-D, No. 4, pp. 514-523, 田丸啓吉，小野寺秀俊	1986.10
「System Design of a Special-Purpose Computer for LSI Design,」	Systems and Computers in Japan, Vol. 18, No. 2, pp. 43-54, Keikichi Tamaru and Hidetoshi Onodera,	1987.2
「A Cyclic Switched Capacitor A-D, D-A Converter,」	Electronics and Communications in Japan, Part 2, Vol. 70, No. 9, pp. 56-65, Hidetoshi Onodera, Tetsuo Tateishi, and Keikichi Tamaru,	1987.9
「A Cyclic A/D Converter That Does Not Require Ratio-Matched Components,」	IEEE Journal of Solid-State Circuits, Vol. 23, No. 1, pp. 152-158, Hidetoshi Onodera, Tetsuo Tateishi, and Keikichi Tamaru,	1988.2
「LSI レイアウトデザインルールチェックに使用する図形演算ハードウェアエンジンのシステム設計」	電子情報通信学会論文誌 A, Vol. J71-A, No. 10, pp. 1861-1869, 坂本守，野村利博，小野寺秀俊，田丸啓吉	1988.10
「Module Generation of a CMOS Op Amp Using a Non-linear Optimization Method,」	Trans. of IEICE Japan, Vol. E71, No. 10, pp. 947-949, Hidetoshi Onodera, Hiroyuki Kanbara, and Keikichi Tamaru,	1988.10
「回路とレイアウトを対応づけたデータ表現とそれを用いたレイアウト設計手法」	電子情報通信学会論文誌 A, Vol. J71-A, No. 12, pp. 2156-2162, 奥田亮輔，小野寺秀俊，田丸啓吉	1988.12
「力学モデルに基づくブロック配置手法」	電子情報通信学会論文誌A, Vol. J72- A, No. 1, pp. 105-113, 小野寺秀俊，田丸啓吉	1989.1
「HILDS:プロセス変更に耐える階層的シンボリックレイアウトシステム」	電子情報通信学会論文誌 A, Vol. J72-A, No. 3, pp. 561-569, 奥田亮輔，小野寺秀俊，田丸啓吉	1989.3
「シフトコンパクション--シンボリックレイアウトの擬 2 次元的コンパクション手法」	電子情報通信学会論文誌 A, Vol. J72-A, No. 8, pp. 1277-1286, 坂本守，小野寺秀俊，田丸啓吉	1989.8
「System Design of the Figure Operation Hardware Engine Used for LSI Layout Design Rule Checking,」	Electronics and Communications in Japan, Part 3, Vol. 72, No. 10, pp. 80-90, M. Sakamoto, H. Onodera, K. Tamaru and T. Nomura,	1989.10
「A Block Placement Procedure Using a Force Model,」	Electronics and Communications in Japan, Part 3, Vol. 72, No. 11, pp. 87-96, Hidetoshi Onodera and Keikichi Tamaru,	1989.11
「A Layout Design Methodology Using Data Description with Correspondence between Circuit and Layout,」	Electronics and Communications in Japan, Part 3, Vol. 72, No. 12, pp. 55-62, R. Okuda, H. Onodera, and K. Tamaru,	1989.12
「OAC: CMOS オペアンプ自動設計システム--システム概要と評価--」	電子情報通信学会論文誌 A, Vol. J73-A, No. 1, pp. 67-76, 小野寺秀俊，神原弘之，田丸啓吉	1990.1
「対称性保持の制約を扱えるレイアウトコンパクションアルゴリズム」	電子情報通信学会論文誌 A, Vol. J73-A, No. 3, pp. 536-543, 奥田亮輔，佐藤寿倫，小野寺秀俊，田丸啓吉	1990.3
「Operational-Amplifier Compilation with Performance Optimization,」	IEEE Journal of Solid-State Circuits, Vol. 25, No. 2, pp. 466-473, Hidetoshi Onodera, Hiroyuki Kanbara, and Keikichi Tamaru,	1990.4
「Shiftcompaction -- Quasi-two- dimensional Compaction Method for Symbolic Layout,」	Electronics and Communications in Japan, Part 3, Vol. 73, No. 8, pp. 40-51,Makoto Sakamoto, Hidetoshi Onodera, and Keikichi Tamaru,	1990.8
「アナログ回路の合成と最適化 (招待論文)」	電子情報通信学会論文誌 A, Vol. J74-A, No. 2, pp. 179-186	1991.2
「CMOS オペアンプ自動設計システムOAC における自動回路設計手法--回路構造と素子概略値の決定--」	電子情報通信学会論文誌 A, Vol. J74-A, No. 2, pp. 277-286, 音羽克則，安田岳雄，小野寺秀俊，田丸啓吉	1991.2
「ビルディングブロックレイアウトのための分枝限定配置手法」	電子情報通信学会論文誌 A, Vol. J75-A, No. 9, pp. 1487-1495, 小野寺秀俊，谷口陽，田丸啓吉	1992.5
「Improved Method of Loss Measurement for Optical Waveguides by Use of a Rectangular Glass Probe,」	Applied Optics, Vol. 31, No. 12, pp. 2078-2084, Awai, H. Onodera, Y. Choi, M. Nakajima and J. Ikenoue,	1992.6
「Guide: アナログ回路設計手順保存・再利用システム」	電子材料, Vol. 32, No. 1, pp. 136-137, 森江隆史, 小野寺秀俊, 田丸啓吉	1993.1
「A Bit-Parallel Block-Parallel Functional Memory Type Parallel Processor Architecture,」	IEICE Trans. Electronics, Vol. E76-C, No. 7, pp. 1151-1158, K. Kobayashi, K. Tamaru, H. Yasuura, and H. Onodera,	1993.7
「Hardware Architecture for Kohonen Network,」	IEICE Trans. Electronics, Vol. E76-C, No. 7, pp. 1159-1166, H. Onodera, K. Takeshita, and K. Tamaru,	1993.7
「Branch-and-Bound Placement for Building Block Layout,」	Electronics and Communications in Japan, Part 3, Vol. 76, No. 7, pp. 15-26,H. Onodera, Y. Taniguchi, and K. Tamaru,	1993.7
「アナログ回路設計手順の保存・再利用化手法」	電子情報通信学会論文誌 A, Vol. J76-A, No. 10, pp. 1457-1464, 森江隆史, 小野寺秀俊, 田丸啓吉	1993.10
「A Method for Analog Circuit Design That Store and Reuses Design Procedures,」	Electronics and Communications in Japan, Part 3, Vo.. 77, No. 3, pp. 87-96,Takashi Morie, Hidetoshi Onodera, and Keikichi Tamaru,	1994.3
「Experiments with Power Optimization in Gate Sizing,」	IEICE Trans. Fundamentals, Vol. E77-A, No. 11, pp. 1913-1916, Guangqin Chen, Hidetoshi Onodera, and Keikichi Tamaru,	1994.11
「Development of Module Generators from Extracted Design Procedures,」	IEICE Trans. Fundamentals, Vol. E78-A, No. 2, pp. 160-168, Takashi Morie, Hidetoshi Onodera, and Keikichi Tamaru,	1995.2
「Compaction with Shape Optimization and its Application to Layout Recycling,」	IEICE Trans. Fundamentals, Vol. E78-A, No. 2, pp. 169-176, Kazuhisa Okada, Hidetoshi Onodera, and Keikichi Tamaru,	1995.2
「Model-Adaptable MOSFET Parameter Extraction System,」	IEICE Trans. Fundamentals, Vol. E78-A, No. 5, pp. 569-572, M. Kondo, H. Onodera, and K. Tamaru,	1995.5
「中間モデルを用いたモデル依存性の小さいMOSFET パラメータ抽出手法」	電子情報通信学会論文誌 A, Vol. J78-A, No. 9, pp. 1133-1141, 近藤正樹, 小野寺秀俊, 田丸啓吉	1995.9
「Estimation of Short-Circuit Power dissipation for Static CMOS Gates,」	IEICE Trans. Fundamentals, Vol. E79-A, No. 3, pp. 304 - 311, Akio Hirata, Hidetoshi Onodera, and Keikichi Tamaru,	1996.3
「A Current Mode Cyclic A/D Converter with Submicron Processes,」	IEICE Trans. Fundamentals, Vol. E80-A, No. 2, pp. 360 - 364, Masaki Kondo, Hidetoshi Onodera, and Keikichi Tamaru,	1997.2
「Performance-driven macro-block placer for architectural evaluation of ASIC designs,」	IEE Proc. Circuits Devices Syst., Vol. 144, No. 3, pp. 190 - 194, V. Moshnyaga, Y. Mori, H. Onodera, and K. Tamaru,	1997.6
「A Memory-Based Parallel Processor for Vector Quantization: FMPP-VQ,」	IEICE Trans. Electronics, Vol. E80-C, No. 7, pp. 970 - 975, K. Kobayashi, M. Kinoshita, H. Onodera, and K. Tamaru,	1997.7
「Analytical Formulas of Output Waveform and Short-Circuit Power Dissipation for Static CMOS Gates Driving a CRC π Load,」	IEICE Trans. Fundamentals, Vol. E81-A, No. 3, pp. 462 - 469, Akio Hirata, Hidetoshi Onodera, and Keikichi Tamaru,	1998.3
「アナログ回路設計方法の再利用率向上手法-設計制約とパラメータの確信度の保存と再利用」	電子情報通信学会論文誌 A, Vol. J81-A, No. 3, pp. 397-407, 森江隆史, 小野寺秀俊, 田丸啓吉	1998.3
「An LSI for Low Bit-Rate Image Compression Using Vector Quantization,」	IEICE Trans. Electronics, Vol. E81-C, No. 5, pp. 718 - 724, K. Kobayashi, N. Nakamura, K. Terada, H. Onodera, and K. Tamaru,	1998.5
「Memory Based Architecture and its Implementation Scheme Named Bit-Parallel Block-Parallel Functional Memory Type Parallel Processor BPBP FMPP,」	Computers & Electrical Engineering, Vol. 24, pp. 17 - 31, K. Tamaru, K. Kobayashi, and H. Onodera,	1998.1
「Model-Adaptable MOSFET Parameter Extraction Method Using an Intermediate Model,」	IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, Vol. 17, No. 5, pp. 400 - 405, Masaki Kondo, Hidetoshi Onodera, and Keikichi Tamaru,	1998.5
「Estimation of Propagation Delay Considering Short-Circuit Current for Static CMOS Gates,」	IEEE Trans. Circuits and Systems-I: Fundamental Theory and Applications, Vol. 45, No. 11, pp. 1194 - 1198, Akio Hirata, Hidetoshi Onodera, and Keikichi Tamaru,	1998.11
「中間モデルを用いたMOSFET の統計的モデル化手法」	電子情報通信学会論文誌 A, Vol. J81-A, No. 11, pp. 15550-1563, 近藤正樹, 小野寺秀俊, 田丸啓吉	1998.11
「A Power and Delay Optimization Method Using Input Reordering in Cell-Based CMOS Circuits,」	IEICE Trans. Fundamentals, Vol. E82-A, No. 1, pp. 159-166, M. Hashimoto, H. Onodera, K. Tamaru,	1999.1
「Layout Dependent Matching Analysis of CMOS Circuits,」	IEICE Trans. Fundamentals, Vol. E82-A, No. 2, pp. 348-355, K. Okada, H. Onodera, K. Tamaru,	1999.2
「A Real-Time Low-Rate Video Compression Algorithm Using Multi-Stage Hierarchical Vector Quantization,」	IEICE Trans. Fundamentals, Vol. E82-A, No. 2, pp. 215-222, K. Kobayashi, K. Terada, H. Onodera, K. Tamaru,	1999.2
「グリッチの削減を考慮したゲート寸法最適化による消費電力削減手法」	情報処理学会論文誌, Vol. 40, No. 4, pp. 17070-1716, 橋本昌宜, 小野寺秀俊, 田丸啓吉	1999.4
「抵抗分を含む負荷を駆動するCMOS 論理回路のゲート遅延時間計算手法」	情報処理学会論文誌, Vol. 40, No. 4, pp. 16790-1686, 平田昭夫, 近藤友一, 小野寺秀俊, 田丸啓吉	1999.4
「P2Lib: スタンダードセルライブラリ自動生成システム」	情報処理学会論文誌, Vol. 40, No. 4, pp. 1660-1669, 小野寺秀俊, 平田昭夫, 北村晃男, 小林和淑, 田丸啓吉	1999.4
「ベクトル合成モデルによる集積回路遅延特性のワーストケース解析」	情報処理学会論文誌, Vol. 41, No. 4, pp. 9270-934, 藤田智弘, 小野寺秀俊	2000.4
「A Method for Linking Process-Level Variability to System Performances,」	IEICE Trans. Fundamentals, Vol. E83-A, No. 12, pp. 2591-2599, T. Fujita and H. Onodera,	2000.12
「Architecture and Performance Evaluation of a New Functional Memory: Functional Memory for Addition,」	IEICE Trans. Fundamentals, Vol. E83-A, No. 12, pp. 2400-2408, K. Kobayashi, M. Yamaoka, Y. Kobayashi, H. Onodera, K. Tamaru,	2000.12
「A Performance Optimization Method by Gate Resizing Based on Statistical Static Timing Analysis,」	IEICE Trans. Fundamentals, Vol. E83-A, No. 12, pp. 2558- 2568, M. Hahsimoto and H. Onodera,	2000.12
「Statistical Modeling of Device Characteristics with Systematic Variability,」	IEICE Trans. on Fundamentals, Vol. E84-A, No. 2, pp. 529-536, K. Okada and H. Onodera,	2001.2
「A Low-Power High-Performance Vector-Pipeline DSP for Low-Rate Videophones,」	IEICE Trans. on Electronics, Vol. E84-C, No. 2, pp. 193-201, K. Kobayashi, M. Eguchi, T. Iwahashi, T. Shibayama, X. Li, K. Takai, H. Onodera,	2001.2
「A Hierarchical Statistical Optimization Method Driven by Constraint Generation Based on Mahalanobis Distance,」	IEICE Trans. Fundamentals, Vol. E84-A, No. 3, pp. 727-734, T. Fujita and H. Onodera,	2001.3
「Post-Layout Transistor Sizing for Power Reduction in Cell-Base Design,」	IEICE Trans. on Fundamentals, Vol. E84-A, No. 11, pp. 2769-2777, M. Hashimoto and H. Onodera,	2001.11
「A Dynamically Phase Adjusting PLL for Improvement of Lock-up Performance,」	IEICE Trans. on Fundamentals, Vol. E84-A, No. 11, pp. 2793-2801, T. Yasuda, H. Fujita, H. Onodera,	2001.11
「トランジスタ特性におけるチップ内ばらつきのモデル化手法」	情報処理学会論文誌, Vol. 43, No. 5, pp. 1330-1337, 岡田健一, 小野寺秀俊	2002.5
「VLSI 配線の伝送線路特性を考慮した駆動力決定手法」	情報処理学会論文誌, Vol. 43, No. 5, pp. 1338-1347, 土谷亮, 橋本昌宜, 小野寺秀俊	2002.5
「Increase in Delay Uncertainty by Performance Optimization,」	IEICE Trans. on Fundamentals, Vol. E85-A, No. 12, pp. 2799-2802, Masanori Hashimoto and Hidetoshi Onodera,	2002.12
「Realistic Delay Calculation Based on Measured Intra-Chip and Inter-Chip Variabilities with the Size Dependence,」	IEICE Trans. on Fundamentals, Vol. E86-A, No. 4, pp. 746-751, K. Okada and H. Onodera,	2003.4
「機能特化型プロセッサアレーによるSoC アーキテクチャの提案」	電子情報通信学会論文誌 エレクトロニクス分冊, Vol. J86-C, No. 8, pp. 7900-798, 湯山洋一, 荒本雅夫, 高井幸輔, 小林和淑, 小野寺秀俊	2003.8
「Statistical Gate-Delay Modeling with Intra-Gate Variability,」	IEICE Trans. on Fundamentals, Vol. E86-A, No. 12, pp. 2914-2922, K. Okada, K. Yamaoka, H. Onodera,	2003.12
「Crosstalk Noise Estimation for Generic RC Trees,」	IEICE Trans. on Fundamentals, Vol. E86-A, No. 12, pp. 2965-2973, M. Hashimoto, M. Takahashi, H. Onodera,	2003.12
「Representative Frequency for Interconnect R(f)L(f)C Extraction,」	IEICE Trans. on Fundamentals, Vol. E86-A, No. 12, pp. 2942-2951, A.Tsuchiya, M. Hashimoto, H. Onodera,	2003.12
「Experimental Study on Cell-Base High-Performance Datapath Design,」	IEICE Trans. on Fundamentals, Vol. E86-A, No. 12, pp. 3204-3207, M. Hashimoto, Y. Hayashi, H. Onodera,	2003.12
「An Efficient Motion Estimation Algorithm Using a Gyro Sensor,」	IEICE Trans. on Fundamentals, Vol. E87-A, No. 3, pp. 530-538, K. Kobayashi, R. Nakanishi, H. Onodera,	2004.3
「A Comprehensive Simulation and Test Environment for Prototype VLSI Verification,」	IEICE Trans. on Information and Systems, Vol. E87-D, No. 3, pp. 630-636, K. Kobayashi and H. Onodera,	2004.3
「Instruction-Level Power Estimation Method by Considering Hamming Distance of Registers,」	IEICE Trans. on Fundamentals, Vol. E87-A, No. 4, pp. 823-829, A.Higuchi, K. Kobayashi, H. Onodera,	2004.4
「Equivalent Waveform Propagation for Static Timing Analysis,」	IEEE Trans. on CAD, Vol. 23, No. 4, pp. 498-508, M. Hashimoto, Y. Yamada, H. Onodera,	2004.4
「Variable RF Inductor on Si CMOS Chip,」	Japanese Journal of Applied Physics,Vol. 43, pp. 2293- 2296, H. Sugawara, Y. Yokoyama, S. Gomi, H. Ito, K. Okada, H. Hoshino, H. Onodera, K. Masu,	2004.5
「Design Optimization Methodology for On-Chip Spiral Inductors,」	IEICE Trans. on Electronics, Vol. E87-C, No. 6, pp. 933-941, K. Okada, H. Hoshino, H. Onodera,	2004.6
「Crosstalk Noise Optimization by Post-Layout Transistor Sizing,」	IEICE Trans. on Fundamentals, Vol. E87-A, No. 12, pp. 3251-3257, M. Hashimoto and H. Onodera,	2004.12
「Statistical Parameter Extraction for Intra- and Inter-Chip Variabilities of Metal-Oxide-Semiconductor Field-Effect Transistor Characteristics,」	Japanese Journal of Applied Physics, Vol. 44, pp. 131-134, K. Okada and H. Onodera,	2005.2
「A Performance Prediction of Clock Generation PLLs: A Ring Oscillator Based PLL and an LC Oscillator Based PLL,」	IEICE Trans. on Electronics, Vol. E88-C, No. 3, pp. 437-444, T. Miyazaki, M. Hashimoto, H. Onodera	2005.3
「Performance Limitation of On-Chip Global Interconnects for High-Speed Signaling,」	IEICE Trans. on Fundamentals, Vol. E88-A, No. 4, pp. 885-891, A.Tsuchiya, M. Hashimoto, H. Onodera	2005.4
「A resource-Shared VLIW Processor for Low-power On- Chip Multiprocessing in the Nanometer Era,」	IEICE Trans. on Electronics, Vol. E88-C, No. 4, pp. 552-558, K. Kobayashi, M. Aramoto, H. Onodera,	2005.4
「Acquisition-time estimation for over 10 Gbit/s clock and data recovery ICs,」	Electronics Letters, Vol. 41, No. 23, pp. 1273-1275, K. Kishine and H. Onodera,	2005.11
「Effects of On-Chip Inductance on Power Distribution Grid,」	IEICE Trans Fundamentals, Vol. E88-A, No. 12, pp. 3564-3572, Atsushi Muramatsu, Masanori Hashimoto, Hidetoshi Onodera,	2005.12
「Statistical Analysis of Clock Skew Variation in H-Tree Structure,」	IEICE Trans. Fundamentals, Vol. E88-A, No. 12, pp. 3375- 3381, Masanori Hashimoto, Tomonori Yamamoto, Hidetoshi Onodera,	2005.12
「Successive Pad Assignment for Minimizing Supply Voltage Drop,」	IEICE Trans. Fundamentals, Vol. E88-A, No. 12, pp. 3429-3436, Takashi Sato, Masanori Hashimoto, Hidetoshi Onodera,	2005.12
「Alternative Self-Shielding for High-Speed and Reliable On-Chip Global Interconnect,」	IEICE Trans. Fundamentals, Vol. E89-C, No. 3, pp. 327-333, Yoichi Yuyama, Akira Tsuchiya, Kazutoshi Kobayashi, Hidetoshi Onodera,	2006.3
「Variability: Modeling and Its Impact on Design」	IEICE Trans. Electron., Vol. E89-C, No. 3, pp. 342 -- 348,	2006.3
「A Leakage Reduction Scheme for Sleep Transistors with Decoupling Capacitors in the Deep Submicron Era,」	IEICE Trans. on Electronics, Vol. E89-C, No. 6, pp. 838-843, K. Kobayashi, A. Higuchi, H. Onodera,	2006.6
「Si-Substrate Modeling toward Substrate-Aware Interconnect Resistance and Inductance Extraction in SoC Design,」	IEICE Trans. on Fundamentals, Vol. E89-A, No. 12, pp. 3560-3568, Toshiki Kanamoto, Tatsuhiko Ikeda, Akira Tsuchiya, Hidetoshi Onodera, Masanori Hashimoto,	2006.12
「Interconnect RL Extraction Based on Transfer Characteristics of Transmission-Line,」	IEICE Trans. on Fundamentals, Vol. E89-A, No. 12, pp. 3585-3593, Akira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera,	2006.12
「A 90 nm LUT Array for Speed and Yield Enhancement by Utilizing Within-Die Delay Variations,」	IEICE Trans. on Electronics, Vol. E90-C, No. 4, pp. 699-707, Kazuya Katsuki, Manabu Kotani, Kazutoshi Kobayashi, Hidetoshi Onodera,	2007.4
「Optimal Termination of On-Chip Transmission-Lines for High-Speed Signaling,」	IEICE Trans. on Electronics, Vol. E90-C, No. 6, pp. 1267-1273, Akira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera,	2007.6
「Low-Power Design of CML Driver for On-Chip Transmission-Lines using Impedance-Unmatched Driver,」	IEICE Trans. on Electronics, Vol. E90-C, No. 6, pp. 1274-1281, Takeshi Kuboki, Akira Tsuchiya, Hidetoshi Onodera,	2007.6
「A 90nm 48x48 LUT-Based FPGA Enhancing Speed and Yield Utilizing Within-Die Delay Variations,」	IEICE Trans. on Electronics, Vol. E90-C, No. 10, pp. 1919-1926, (Best Paper Award), K. Kobayashi, K. Katsuki, M. Kotani, Y. Sugihara, Y. Kume, H. Onodera,	2007.10
「Timing Analysis Considering Spatial Power/Ground Level Variation,」	IEICE Trans. on Electronics, Vol. E90-A, No. 12, pp. 2661-2668, Masanori Hashimoto, Junji Yamaguchi, Hidetoshi Onodera,	2007.12
「Manufacturability-Aware Design of Standard Cells,」	IEICE Trans. on Electronics, Vol. E90-A, No. 12, pp. 2682-2960, Hirokazu Muta and Hidetoshi Onodera,	2007.12
「Timing Analysis Considering Temporal Supply Voltage Fluctuation,」	IEICE Trans. on Information and Systems, Vol. E91- D, No. 3, pp. 655-660, Masanori Hashimoto, Junji Yamaguchi, Takashi Sato, Hidetoshi Onodera,	2008.3
「Accurate Estimation of the Worst-case Delay in Statistical Static Timing Analysis,」	IPSJ Trans. on System LSI Design Methodology, Vol. 1, pp. 116-125, Haruhiko Terada, Takayuki Fukuoka, Akira Tsuchiya, Hidetoshi Onodera,	2008.8
「Analytical Model of Static Noise Margin in CMOS SRAM for Variation Consideration,」	IEICE Trans. Electron, Vol. E91-C, No. 9, pp. 1488- 1500, Hirofumi Shinohara, Koji Nii, Hidetoshi Onodera,	2008.9
「Patterned Floating Dummy Fill for On-Chip Spiral Inductor Considering the Effect of Dummy Fill,」	IEEE Trans. on Microwave Theory and Techniques, Vol. 56, No. 12, pp. 3217-3222, Akira Tsuchiya and Hidetoshi Onodera,	2008.12
「Low-jitter design method based on ωn-domain jitter analysis for 10 Gbit/s clock and data recovery ICs,」	Electronics Letters, Vol. 45, No. 16, pp. 808-809, K. Kishine, H. Inaba, Ma. Nakamura, Mi. Nakamura, Y. Ohtomo, H. Onodera,	2009.7
「Statistical Gate Delay Model for Multiple Input Switching,」	IEICE Trans. on Fundamentals, Vol. E92-A, No. 12, pp. 3070-3078, Takayuki Fukuoka, Akira Tsuchiya, Hidetoshi Onodera,	2009.12
「Effect of Regularity-Enhanced Layout on Variability and Circuit Performance of Standard Cells,」	IPSJ Trans. on System LSI Design Methodology, Vol. 3, pp. 130-139, Hiroki Sunagawa, Haruhiko Terada, Akira Tsuchiya, Kazutoshi Kobayashi, Hidetoshi Onodera,	2010.2
「An Area/Delay Efficient Dual-Modular Flip-Flop with Higher SEU/SET Immunity,」	IEICE Trans. on Electronics, Vol. E93-C, No. 3, pp. 340-346, Jun Furuta, Kazutoshi Kobayashi, Hidetoshi Onodera,	2010.3
「A 65 nm Complementary Metal-Oxide-Semiconductor 400 ns Measurement Delay Negative-Bias-Temperature-Instability Recovery Sensor with Minimum Assist Circuit,」	Japanese Journal of Applied Physics, Vol. 50, pp. 04DE06, Takashi Matsumoto, Hiroaki Makino, Kazutoshi Kobayashi, Hidetoshi Onodera,	2011.4
「Variation-Tolerance of a 65-nm Error-Hardened Dual-Modular-Redundancy Flip-Flop Measured by Shift-Register-Based Monitor Structures,」	IEICE Trans. on Fundamentals, Vol. E94-A, No. 12, pp. 2669- 2675, C. Hamanaka, R. Yamamoto, J. Furuta, K. Kubota, K. Kobayashi, H. Onodera,	2011.11
「An Area-efficient 65 nm Radiation-Hard Dual-Modular Flip-Flop to Avoid Multiple Cell Upsets,」	IEEE Trans. on Nuclear Science, Vol. 58, No. 6, pp. 3053 - 3059, R. Yamamoto, C. Hamanaka, J. Furuta, K. Kobayashi, H. Onodera,	2011.11
「Area-effective inductive peaking with interwoven inductor for high-speed Laser-Diode Driver for Optical Communication System,」	IEICE Trans. on Fundamentals, Vol. E95-A, No. 2, pp. 479-486, Takeshi Kuboki, Yusuke Ohtomo, Akira Tsuchiya and Hidetoshi Onodera,	2012.2
「Multicore Large-Scale Integration Life-time Extension by Negative Bias Temperature Instability Recovery-Based Self-Healing,」	Japanese Journal of Applied Physics, Vol. 51, pp. 04DE02, T. Matsumoto, H. Makino, K. Kobayashi, and H. Onodera,	2012.4
「Area-Efficient Reconfigurable-Array-Based Oscillator for Standard Cell Characterization,」	IET Circuits, Devices & Systems, Vol. 6, No. 6, pp. 429-436, Bishnu Prasad Das and Hidetoshi Onodera,	2012.11
「Variation-sensitive Monitor Circuits for Estimation of Global Process Parameter Variation,」	IEEE Trans. Semiconductor Manufacturing, Vol. 25, No. 4, pp. 571-580, Islam A.K.M. Mahfuzul, Akira Tsuchiya, Kazutoshi Kobayashi, Hidetoshi Onodera,	2012.11
「Area-Efficient Reconfigurable-Array-Based Oscillator for Standard Cell Characterization,」	IET Circuits, Devices & Systems, vol. 6, No. 6, pp. 429-436, Bishnu Prasad Das and Hidetoshi Onodera,	2012.12
「Variation-sensitive Monitor Circuits for Estimation of Global Process Parameter Variation,」	IEEE Trans. Semiconductor Manufacturing, vol. 25, No. 4, pp. 571-580, Islam A.K.M. Mahfuzul, Akira Tsuchiya, Kazutoshi Kobayashi, Hidetoshi Onodera,	2012.12
「再構成可能ディペンダブルVLSI プラットホーム」	電子情報通信学会誌, Vol. 96, No. 2, pp. 950-99, 密山幸男, 尾上孝雄, 小野寺秀俊	2013.2
「Effects of Neutron-Induced Well Potential Perturbation for Multiple Cell Upset of Flip-Flops in 65 nm,」	IEEE Trans. on Nuclear Science, vol. 60, no. 1, pp. 213-218, J. Furuta, R. Yamamoto, K. Kobayashi, and H. Onodera,	2013.2
「Impact of Body-Biasing Technique on Random Telegraph Noise Induced Delay Fluctuation,」	Japanese Journal of Applied Physics, vol. 52, No. 4, 04CE05, T. Matsumoto, K. Kobayashi, H. Onodera,	2013.4
「Inhomogeneous Ring Oscillator for Within-Die Variability and RTN Characterization,」	IEEE Transactions on Semiconductor Manufacturing, Vol. 26, No. 3, pp. 296-305, S. Fujimoto, A.K.M.M. Islam, T. Matsumoto, H. Onodera,	2013.8
「A Ring Oscillator With Calibration Circuit for On-Chip Measurement of Static IR-drop,」	IEEE Transactions on Semiconductor Manufacturing, Vol. 26, No. 3, pp. 306-313, Shinichi Nishizawa and Hidetoshi Onodera,	2013.8
「On-Chip Detection of Process Shift and Process Spread for Post-Silicon Diagnosis and Model-Hardware Correlation,」	IEICE Transactions on Information and Systems, vol. E96-D, no. 9, pp. 1971- 1979, A.K.M. Mahfuzul Islam, and Hidetoshi Onodera,	2013.9
「特性ばらつき概説」	日本信頼性学会誌, Vol. 35, No. 8, pp. 445-446	2013.12
「特性ばらつきの診断と補償」	日本信頼性学会誌, Vol. 35, No. 8, p. 447	2013.12
「Area-efficient Reconfigurable Ring Oscillator for Characterization of Static and Dynamic Variations,」	Japan Journal of Applied Physics, vol 53, no 4S, pp. 04EE08-1 - 04EE08-8, A.K.M. Mahfuzul Islam, and Hidetoshi Onodera,	2014.4
「Radiation-Hardened PLL with a Switchable Dual Modular Redundancy Structure,」	IEICE Transactions on Electronics, to appear, vol. E97-C, no. 4, SinNyoung Kim, Akira Tsuchiya, and Hidetoshi Onodera,	2014.4
「A Body Bias Generator with Low Supply Voltage for Within-die Variability Compensation,」	IEICE Trans. on Fundamentals, Vol. E97-A, No. 3, pp. 734 -740, DOI:10.1587/transfun.E97.A.734, Norihiro KAMAE, Akira TSUCHIYA, Hidetoshi ONODERA,	2014.3
「Analysis of Radiation-Induced Clock- Perturbation in Phase-Locked Loop,」	IEICE Trans. on Fundamentals, Vol. E97-A, No. 3, pp. 768- 776, DOI:10.1587/transfun.E97.A.768, SinNyoung Kim, Akira Tsuchiya, and Hidetoshi Onodera,	2014.3
「On-chip Measurement of Rise/Fall Gate Delay Using Reconfigurable Ring Oscillator,」	IEEE Trans. on Circuits and Systems II, Vol. 61, No. 3, pp. 183- 187, DOI:10.1109/TCSII.2013.22961, Bishnu Prasad Das, Hidetoshi Onodera,	2014.3
「Radiation-Hardened PLL with a Switchable Dual Modular Redundancy Structure,」	IEICE Trans. on Electronics, Vol. E97-C, No. 4, pp. 325 - 331, DOI:10.1587/transele.E97.C.325,SinNyoung Kim, Akira Tsuchiya, and Hidetoshi Onodera,	2014.4
「Area-efficient reconfigurable ring oscillator for device and circuit level characterization of static and dynamic variations,」	Japanese Journal of Applied Physics, Vol. 53, No. 4S, pp. 04EE08-1 - 04EE08-8, DOI:10.7567/JJAP.53.04EE08, A.K.M. Mahfuzul Islam and Hidetoshi Onodera,	2014.4
「A Low-Power and Area-Efficient Radiation-Hard Redundant Flip-Flop, DICE ACFF, in a 65 nm Thin-BOX FD-SOI,」	IEEE Trans. on Nuclear Science, Vol. 61, No. 4 part1, pp. 1881-1888, DOI:10.1109/TNS.2014.2318326, K. Kobayashi, K. Kubota, M. Masuda, Y. Manzawa, J. Furuta, S. Kanda, H. Onodera,	2014.8
「Dependence of Cell Distance and Well-Contact Density on MCU Rates by Device Simulations and Neutron Experiments in a 65-nm Bulk Process,」	IEEE Trans. on Nuclear Science, Vol. 61, No. 4 part1, pp. 1583-1589, DOI:10.1109/TNS.2014.2314292, K. Zhang, J. Furuta, K. Kobayashi, H. Onodera,	2014.8
「Reliability-Configurable Mixed-Grained Reconfigurable Array Supporting C-Based Design and Its Irradiation Testing,」	IEICE Trans. Fundamentals, Vol. E97-A, No. 12, pp. 2518 - 2529, DOI:10.1587/transfun.E97.A.2518, Hiroaki Kounoura, Dawood Alnajjar, Yukio Mitsuyama, Hajime Shimada, Kazutoshi Kobayashi, Hiroyuki Kanbara, Hiroyuki Ochi, Takashi Imagawa, Kazutoshi Wakabayashi, Hasanori Hashimoto, Takao Onoye, Hidetoshi Onodera,	2014.12
「Frequency-Independent Warning Detection Sequential for Dynamic Voltage and Frequency Scaling in ASICs」	IEEE Trans. on Very Large Scale Integration (VLSI) Sytems, Vol. 22, No. 12, pp. 2535-2548, DOI:10.1109/TVLSI.2013.2296033, Bishnu Prasad Das and Hidetoshi Onodera,	2014.12
「Impact of Cell Distance and Well-contact Density on Neutron-induced Multiple Cell Upsets,」	IEICE Trans. Electron., Vol. E98-4, No. 4, pp. 298 - 303, DOI:10.1587/transele.E98.C.298, Jun Furuta, Kazutoshi Kobayashi, Hidetoshi Onodera,	2015.4
「A Multi-Rate Burst-Mode CDR Using a GVCO With Symmetric Loops for Instantaneous Phase Locking in 65-nm CMOS,」	IEEE Trans. on Circuits and Systems I, Vol. 62, No. 5, pp. 1288-1295, DOI:10.1109/TCSI.2015.2416812, K. Kishine, H. Inaba, H. Inoue, M. Nakamura, A. Tsuchiya, H. Katsurai, H. Onodera,	2015.5
「A Forward/Reverse Body Bias Generator with Wide Supply- Range down to Threshold Voltage,」	IEICE Trans. on Electronics, Vol. E98-C, No. 6, pp. 504-511, N. Kamae, A. Tsuchiya, H. Onodera,	2015.6
「Statistical Timing Modeling Based on a Log-normal Distribution Model for Near-Threshold Circuit Optimization,」	IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E98-A, No. 7, pp. 1455-1466, DOI:10.1587/transfun.E98.A.1455, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera,	2015.7
「Layout Generator with Flexible Grid Assignment for Area Efficient Standard Cell,」	IPSJ Trans. on System LSI Design Methodology, Vol. 8, pp. 131 - 135, DOI:10.2197/ipsjtsldm.8.131, Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera,	2015.8
「Wide-Supply-Range All-Digital Leakage Variation Sensor for On-Chip Process and Temperature Monitoring,」	IEEE Journal of Solid-State Circuits, Vol. 50, No. 11, pp. 2475- 2490, DOI:10.1109/JSSC.2015.2461598, A.K. M. Mahfuzul Islam, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera,	2015.11
「Analytical Stability Modeling for CMOS Latches in Low Voltage Operation,」	IEICE Transactions on Fundamentals, Vol. E99- A, No. 12, pp. 2463-2472, Tatsuya Kamakari, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera,	2016.12
「Area-Efficient Fully Digital Memory Using Minimum Height Standard Cells for Near-Threshold Voltage Computing,」	Integration, the VLSI Journal, Elsevier, DOI:10.1016/j.vlsi.2017.07.001, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera,	2017.7
「Statistical Analysis and Modeling of Random Telegraph Noise Based on Gate Delay Measurement,」	IEEE Trans. on Semiconductor Manufacturing, Vol. 30, No. 3, pp. 216 - 226, DOI:10.1109/TSM.2017.2715168, A.K.M. Mahfuzul Islam, Tatsuya Nakai, Hidetoshi Onodera,	2017.8
「A Minimum Energy Point Tracking Algorithm based on Dynamic Voltage Scaling and Adaptive Body Biasing,」	IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E100-A, No. 12, pp. 2776-2784, Shu Hokimoto, Tohru Ishihara, Hidetoshi Onodera,	2017.12
「A Necessary and Sufficient Condition of Supply and Threshold Voltages in CMOS Circuits for Minimum Energy Point Operation,」	IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E100-A, No. 12, pp. 2764 - 2775, DOI:10.1587/transfun.E100.A.2764, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera,	2017.12
「A temperature monitor circuit with small voltage sensitivity using a topology-reconfigurable ring oscillator,」	Japanese Journal of Applied Physics, Vol 57, No. 4S, pp. 04FF09-1 - 04FF09-6, DOI:10.7567/JJAP.57.04FF09, Tadashi Kishimoto, Tohru Ishihara, Hidetoshi Onodera,	2018.3
「Via-Switch FPGA: Highly Dense Mixed-Grained Reconfigurable Architecture With Overlay Via-Switch Crossbars,」	IEEE Trans. on Very Large Scale Integration (VLSI) Systems, Vol. 26, No. 12, pp. 2723- 2736, DOI:10.1109/TVLSI.2018.2812914, H. Ochi, K. Yamaguchi, T. Fujimoto, J. Hotate, T. Kishimoto, T. Higashi, T. Imagawa, R. Doi,M. Tada, T. Sugibayashi, W. Takahashi, K. Wakabayashi, H. Onodera, Y. Mitsuyama, J. Yu, M. Hashimoto,	2018.3
「Minimum Energy Point Tracking with All-Digital On-Chip Sensors,」	ASP Journal of Low Power Electronics, Vol. 14, No. 2, pp. 227- 235, Jun Shiomi, Shu Hokimoto, Tohru Ishihara, and Hidetoshi Onodera,	2018.6
「Sensor Signal Processing Using High-Level Synthesis With a Layered Architecture,」	IEEE Embedded Systems Letters, Vol. 10, No. 4, pp. 119 -122, DOI:10.1109/LES.2018.2797064, Hiroki Hihara, Akira Iwasaki, Masanori Hashimoto, Hiroyuki Ochi, Yukio Mitsuyama, Hidetoshi Onodera, Hiroyuki Kanbara, Kazutoshi Wakabayashi, Tadahiko Sugibayashi, Takashi Takenaka, Hiromitsu Hada, Munehiro Tada, Makoto Miyamura, Toshitsugu Sakamoto,	2018.11
「Design Methodology for Variation Tolerant D-Flip-Flop Using Regression Analysis,」	IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E101-A, No. 12, pp. 2222- 2230, DOI:10.1587/transfun.E101.A.2222, Shinichi NISHIZAWA, Hidetoshi ONODERA,	2018.12
「Circuit Techniques for Device-Circuit Interaction toward Minimum Energy Operation」	IPSJ Trans. on System LSI Design Methodology, Vol.12, pp.2-12, A.K.M. Mahfuzul Islam, Hidetoshi Onodera,	2019.2
「Impact of On-Chip Inductor and Power-Delivery-Network Stacking on Signal and Power Integrity,」	IEICE Trans. on Electronics, Vol. E102-C, No. 7, pp. 573 - 579, DOI:10.1587/transele.2018CTP0007, Akira Tsuchiya, Akitaka Hiratsuka, Toshiyuki Inoue, Keiji Kishine, Hidetoshi Onodera,	2019.7
「A Design Method of a Cell- Based Amplifier for Body Bias Generation,」	IEICE Trans. on Electronics, Vol. E102-C, No. 7, pp. 565-572, DOI:10.1587/transele.2018CTP0014, Takuya Koyanagi, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera,	2019.7
「Low-Power Crossbar Switch With Two-Varistor Selected Complementary Atom Switch (2V-1CAS; Via-Switch) for Nonvolatile FPGA,」	IEEE Trans. on Electron Devices, Vol. 66, No. 8, pp. 3331- 3336,DOI:10.1109/TED.2019.2922352, Naoki Banno, Koichiro Okamoto, Noriyuki Iguchi, Hiroyuki Ochi, Hidetoshi Onodera, Masanori Hashimoto, Tadahiko Sugibayashi, Toshitsugu Sakamoto, and Munehiro Tada,	2019.7
「On-Chip Cache Architecture Exploiting Hybrid Memory Structures for Near-Threshold Computing,」	IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E102-A, No. 12, pp. 1741-1750, Hongjie Xu, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera,	2019.12
「Methods for Reducing Power and Area of BDD-Based Optical Logic Circuits,」	IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, vol E102.A, no 12, pp. 1751-1759, Ryosuke Matsuo, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera, Akihiko Shinya and Masaya Notomi,	2019.12
「Design of a 45 Gb/s, 98 fJ/bit, 0.02 mm2 Transimpedance Amplifier with Peaking-Dedicated Inductor in 65-nm CMOS,」	EICE TRANS. ELECTRON, vol E103.C, no 10, pp. 489 -- 496, DOI: 10.1587/transele.2019CTP0008, Akira TSUCHIYA, Akitaka HIRATSUKA, Kenji TANAKA, Hiroyuki FUKUYAMA, Naoki MIURA, Hideyuki NOSAKA, Hidetoshi ONODERA,	2020.10
「MOSDA: On-chip Memory Optimized Sparse Deep Neural Network Accelerator with Efficient Index Matching,」	IEEE Open Journal of Circuits and Systems, DOI: 10.1109/OJCAS.2020.3035402, Hongjie Xu, Jun Shiomi and Hidetoshi Onodera,	2020.12
Supplemental PDK for ASAP7 Using Synopsys Flow	IPSJ Trans. on System LSI Design Methodology, Vol.14, pp.24-26, Shinichi Nishizawa, Shih-Ting Lin, Yih-Lang Li, Hidetoshi Onodera	2021.08
Via-switch FPGA with transistor-free programmability enabling energy-efficient near-memory parallel computation	Japanese Journal of Applied Physics, Vol 61, SM0804 Masanori Hashimoto, Xu Bai, Naoki Banno, Munehiro Tada, Toshitsugu Sakamoto, Jaehoon Yu, Ryutaro Doi, Hidetoshi Onodera,	2022.10
NCTUcell: A DDA- and Delay-Aware Cell Library Generator for FinFET Structure With Implicitly Adjustable Grid Map	IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, Vol. 41, No. 12, pp. 5568 - 5581, Yih Lang Li, Shih Ting Lin, Shinichi Nishizawa, Hong Yan Su, Ming Jie Fong, Oscar Chen, Hidetoshi Onodera,	2022.12

主な社会的活動等

日本学術会議: 連携会員(2011 -  ).
電子情報通信学会: Trans. Electronics Editor-in-Chief(2006 - 2007)、システムと信号処理サブソサイエティ会長 (2005 - 2006)、VLSI設計技術研究専門委員会委員長(2000 - 2002).
情報処理学会: Trans. System LSI Design Methodology Editor-in-Chief (2007 - 2010)、システムLSI設計技術研究会主査 (2006--2008).
IEEE: CEDA Vice President for Awards (2015 - 2017)、Kansai Section Chair (2013 - 2014)、CASS Kansai Chapter Chair (2007 - 2008)、SSCS Kansai Chapter Chair (2001 - 2002).
IEEE ASP-DAC: Steering Committee Chair (2014 - 2021), General Chair (2007), Program Chair (2006).
IEEE ICCAD: General Chair (2004), Program Chair (2003).
SASIMI Workshop Steering Committee Chair (2013 - 2021).

講義など協力可能なテーマ

集積回路設計技術
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