教員紹介

略歴

所属学会

電子情報通信学会英文論文誌特集号編集委員（1998～1999、2002～2003）
IEEE International Conference on Solid State Devices and Materials プログラム委員（2000）
IEEE International Symposium on Low Power Electronics and Design プログラム委員（2003）
IEEE International Solid-State Circuits Conference(ISSCC)プログラム委員（2005～2008）
電子情報通信学会関西支部評議員（2009～2010）

主な研究業績（著書・論文等）

『電子デバイス活用辞典』	㈱工業調査会 一部を執筆	1994.08
『CMOS 回路設計技術と事例集』	ミマツデータシステム 第２章、第１項を執筆．pp.251-272.	1996
『システム LSI－アプリケーションと技術－』	サイエンスフォーラム 1999 年 7 月 30 日刊行の第 2 篇｢システムの共通要素技術｣ 第 11 章｢基本演算ユニット｣を執筆	1999.07
『半導体LSI技術』	共立出版 第1章および第4～8章を執筆	2012.03
「A GaAs 16K SRAM with a Single 1-V Supply」	IEEE Journal of Solid-State Circuits, Vol.SC-22, No.5, Oct. 1987, pp.699-703. S. Takano, H. Makino, N. Tanino, M. Noda, K. Nishitani, S. Kayano	1987.10
「A 7-ns/850mW GaAs 4-kb SRAM with Little Dependence on Temperature」	IEEE Journal of Solid-State Circuits, Vol.25, No.5, Oct. 1990, pp.1232-1238. H. Makino, S. Matsue, M. Noda, N. Tanino, S. Takano, K. Nishitani, S. Kayano	1990.10
「A 5-ns GaAs 16-kb SRAM」	IEEE Journal of Solid-State Circuits, Vol.26, No.10, Oct. 1991, pp.1399-1406. S. Matsue, H. Makino, M. Noda, H. Nakano, S. Takano, K. Nishitani, S. Kayano	1991.10
「A High-Speed 16-kb GaAs SRAM of Less than 5 ns Using Triple-Level Metal Interconnection」	IEEE Transactions on Electron Devices, Vol.39, No.3, Mar. 1992, pp.494-499. M. Noda, S. Matsue, M. Sakai, K. Sumitani, H. Nakano, T. Oku, H. Makino,K. Nishitani, M. Otsubo	1992.03
「An Application of Air-Bridge Metal Interconnections to High Speed GaAs LSI's」	IEICE Transactions on Electronics, Vol.E75-C, No.10, Oct. 1992, pp.1146-1153. M. Noda, H. Matsuoka, N. Higashisaka, M. Shimada, H. Makino, S. Matsue,Y. Mitsui, K. Nishitani, A. Tada	1992.10
「A BiCMOS Wired-OR Logic」	IEEE Journal of Solid-State Circuits, Vol.30, No.6, Jun. 1995, pp.622-628. Y. Nakase, H. Suzuki, H. Makino, H. Shinohara, K. Mashiko	1995.06
「A 2.6-ns 64-b Fast and Small CMOS Adder」	IEICE Transactions on Electronics, Vol.E79-C, No.4, Apr. 1996, pp.530-537. H. Morinaka, H. Makino, Y. Nakase, H. Suzuki, K. Mashiko, T. Sumi	1996.04
「A Design of High-Speed 4-2 Compressor for Fast Multiplier」	IEICE Transactions on Electronics, Vol.E79-C, No.4, Apr. 1996, pp.538-548. H. Makino, H. Suzuki, H. Morinaka, Y. Nakase, H. Shinohara, K. Mashiko,T. Sumi, Y. Horiba	1996.04
「A 286 MHz 64-b Floating Point Multiplier with Enhanced CG Operation」	IEEE Journal of Solid-State Circuits, Vol.31, No.4, Apr. 1996, pp.504-513. H. Makino, H. Suzuki, H. Morinaka, Y. Nakase, K. Mashiko, T. Sumi	1996.04
“An 8.8-ns 54×54- bit Multiplier with High Speed Redundant Binary Architecture	IEEE Journal of Solid-State Circuits, Vol.31, No.6。	1996.06
「Leading-Zero Anticipation Logic for High-Speed Floating Point Addition」	IEEE Journal of Solid-State Circuits, Vol.31, No.8, Aug. 1996, pp.1157-1164. H. Suzuki, H. Makino, H. Morinaka, Y. Nakase, K. Mashiko, T. Sumi	1996.08
「A Floating-Point Divider Using Redundant Binary Circuits and an Asynchronous Clock Scheme」	IEICE Transactions on Electronics, Vol.E82-C, No.1, Jan. 1999, pp.105-110. H. Suzuki, H. Makino, K. Mashiko	1999.01
「基板バイアス自動制御MT-CMOS 回路技術を用いたLSI の低消費電力化」	電子情報通信学会論文誌 Vol.J82-C-II No.9, Sept. 1999, pp505-512. 荒川 隆彦, 牧野 博之, 辻橋 良樹, 新居 浩二, 森嶋 哉圭, 早川 康, 清水 徹, 岩出 秀平, 小山 健	1999.09
「A 600-MHz 54x54-bit Multiplier with Rectangular-Styled Wallace Tree」	IEEE Journal of Solid-State Circuits, Vol.36, No.2, Feb. 2001, pp.249-257. N. Itoh, Y. Naemura, H. Makino, Y. Nakase, T. Yoshihara, Y. Horiba	2001.02
「Novel VLIW Code Compaction Method for a 3D Geometry Processor」	IEICE Transactions on Electronics, Vol.E84-A, No.11, Nov. 2001, pp.2885-2893. H. Suzuki, H. Kawai, H. Makino, Y. Matsuda	2001.11
｢Realistic Scaling Senario for Sub-100nm Embedded SRAM Based on 3-Dimensional Interconnect Simulation｣	IEICE Transactions on Electronics, Vol.E86-C, No.3, Mar. 2003, pp.439-446. Y. Tsukamoto, T. Kunikiyo, K. Nii, H. Makino, S. Iwade, K. Ishikawa,Y. Inoue, N. Kotani	2003.03
｢A Low Standby Current DSP Core Using Improved ABC-MT-CMOS with Charge Pump Circuit｣	IEICE Transactions on Electronics, Vol.E86-C, No.4, Apr. 2003, pp.597-603. H. Notani, M. Koyama, R. Mano, H. Makino, Y. Matsuda, O. Tomisawa,S. Iwade	2003.04
｢Signal Integrity Design and Analysis for a 400 MHz RISC Microprocessor｣	IEICE Transactions on Electronics, Vol.E86-C, No.4, Apr. 2003, pp.635-642. A. Yamada, Y. nunomura, H. Suzuki, H. Sato, N. Itoh, T. Kagemoto, H. Itoh,T. Kurafuji, N. Yoshioka, J. Nakanishi, H. Notani, R. Akiyama, A. Iwabu,T. Yamanaka, H. Takata, T. Shibagaki, T. Arakawa, H. Makino, O. Tomisawa,S. Iwade	2003.04
｢A Low-Power Microcontroller with Body-Tied SOI Technology｣	IEICE Transactions on Electronics, Vol.E87-C, No.4, April, 2004, pp.563-570. H. Sato, Y. Nunomura, N. Itoh, K. Nii, K. Yoshida, H. Itoh, J. Nakanishi, H. Takata,Y. Nakase, H. Makino, A. Yamada, T. Arakawa, T. Shimizu, Y. Hirano, T. Ipposhi, S. Iwade	2004.04
｢A Wide Range 1.0-3.6V 200Mbps, Push-Pull Output Buffer Using Parasitic Bipolar Transistors｣	IEICE Transactions on Electronics, Vol.E87-C, No.4, April, 2004, pp.571-577. T. Shimada, H. Notani, Y. Nakase, H. Makino, S. Iwade	2004.04
｢A 90-nm Low-Power 32K-Byte Embedded SRAM with Gate Leakage Suppression Circuit for Mobile Applications｣	IEEE Journal of Solid-State Circuits, Vol.39, No.4, April. 2004, pp.684-693. K. Nii, Y. Tsukamoto, T. Yoshizawa, S. Imaoka, Y. Yamagami, T. Suzuki, A. Shibayama,H. Makino, S. Iwade	2004.04
｢Test Structure Measuring Inter- and Intralayer Coupling Capacitance of Interconnection with Subfemto-Farad Resolution｣	IEEE Transaction on Electron Devices, Vol.51, No.5, May 2004, pp.726-735. T. Kunikiyo, T. Watanabe, T. Kanamoto, H. Asazato, M. Shirota, K. Eikyu, Y. Ajioka, H. Makino, K. Ishikawa, S. Iwade, Y. Inoue	2004.05
｢A 65 nm SoC Embedded 6T-SRAM Designed for Manufacturability with Read and Write Operation Stabilizing Circuits｣	IEEE Journal of Solid-State Circuits, Vol.42, No.4, April. 2007, pp.820-829. S. Ohbayashi, M. Yabuuchi, K. Nii, Y. Tsukamoto, S. Imaoka, Y. Oda, T. Yoshihara, M.Igarashi,M. Takeuchi, H. Kawashima, Y. Yamaguchi, K. Tsukamoto, M. Inuishi, H. Makino, K. Ishibashi,H. Shinohara	2007.04
｢A 65 nm Embedded SRAM with Wafer Level Burn-In Mode, Leak-Bit Redundancy and Cu E-trim Fuse for Known Good Die｣	IEEE Journal of Solid-State Circuits, Vol.43, No.1, January 2008, pp.96-108. S. Ohbayashi, M. Yabuuchi, K. Kono, Y. Oda, S. Imaoka, K. Usui, T. Yonezu, T. Iwamoto,K. Nii, Y. Tsukamoto, M. Arakawa, T. Uchida, M. Okada, A. Ishii, T. Yoshihara, H. Makino,K. Ishibashi, H. Shinohara	2008.01
｢A 45-nm Bulk CMOS Embedded SRAM with improved immunity against process and temperature variations｣	IEEE Journal of Solid-State Circuits, Vol.43, No.1, January 2008, pp.180-191. K. Nii, M. Yabuuchi, Y. Tsukamoto, S. Ohbayashi, S. Imaoka, H. Makino, Y. Yamagami, S. Ishikura, T. Terano, T. Oashi, K. Hashimoto, A. Sebe, G. Okazaki, K. Satomi, H. Akamatsu,H. Shinohara	2008.01
｢A 45nm 2port 8T-SRAM using hierarchical replica bitline technique with immunity from simultaneous R/W access issues｣	IEEE Journal of Solid-State Circuits, Vol.43, No.4, April 2008, pp.938-945. S. Ishikura, M. Kurumada, T. Terano, Y. Yamagami, N. Kotani, K. Satomi, K. Nii, M. Yabuuchi,Y. Tsukamoto, S. Ohbayashi, T. Oashi, H. Makino, H. Shinohara, H. Akamatsu	2008.04
｢A Large Scale, Flip-Flop RAM imitating a logic LSI for fast development of process technology｣	IEICE Transactions on Electronics, Vol.E91-C, No.8, August, 2008, pp.1338-1347. M. Fujii, K. Nii, H. Makino, S. Ohbayashi, M. Igarashi, T. Kawamura, M. Yokota, N. Tsuda,T. Yoshizawa, T. Tsutsui, N. Takeshita, N. Murata, T. Tanaka, T. Fujiwara, K. Asahina, M. Okada, K. Tomita, M. Takeuchi, S. Yamamoto, H. Sugimoto, H. Shinohara	2008.08
｢Synchronous Ultra-High-Density 2RW Dual-Port 8T-SRAM with Circumvention of Simultaneous Common-Row-Access｣	IEEE Journal of Solid-State Circuits, Vol.44, No.3, March 2009, pp.977-986. K. Nii, Y. Tsukamoto, M. Yabuuchi, Y. Masuda, S. Imaoka, K. Usui, S. Ohbayashi, H. Makino,H. Shinohara	2009.03
｢Stable adiabatic circuit using advanced series capacitors and time variation of energy dissipation｣	IEICE Electronics Express, Vol.7, No.9, May 2010, pp.640-646. S. Nakata, S. Mutoh, H. Makino, M. Miyama, Y. Matsuda	2010.05
｢Reexamination of SRAM Cell Write Margin Definitions in view of Predicting the Distribution｣	IEEE Transactions on Circuits and Systems-II Express Briefs, Volume 58, Issue 4, April 2011, pp.230-234. H. Makino, S. Nakata, H. Suzuki, S. Mutoh, M. Miyama, T. Yoshimura, S. Iwade Y. Matsuda	2011.04
”Utilising the normal distribution of the write noise margin to easily predict the SRAM write yield”	IET Circuits、 Devices & Systems, Volume 6, Issue 4。	2012.07
｢Improved Evaluation Method for the SRAM Cell Write Margin by Word Line Voltage Acceleration｣	Circuits and Systems in Online Journal of Scientific Research Publishing (SCIRP), Volume 3, No. 3, July 2012, pp.242-251.doi: 10.4236/cs.2012.33034 Hiroshi Makino, Naoya Okada, Tetsuya Matsumura, Koji Nii, Tsutomu Yoshimura, Shuhei Iwade, and Yoshio Matsuda	2012.07
｢General Stability of Stepwise Waveform of an Adiabatic Charge Recycling Circuit With Any Circuit Topology｣	IEEE Transactions on Circuits and Systems-I:Regular Papers, Volume 59, Issue 10, October 2012, pp.2301-2314. doi: 10.1109/TCSI.2012.2189054 Shunji Nakata, Ryota Honda, Hiroshi Makino, Shin’ichiro Mutoh, Masayuki Miyama, and Yoshio Matsuda	2012.10
｢Analysis of Pull-in Range Limit by Charge Pump Mismatch in a Linear Phase-locked Loop｣	IEEE Transactions on Circuits and Systems-I:Regular Papers, Volume 60, Issue 4, April 2013, pp.896-907. Doi: 10.1109/TCSI.2012.2215393 Tsutomu Yoshimura, Shuhei Iwade, Hiroshi Makino, and Yoshio Matsuda	2013.04
｢ANALYSIS OF VOLTAGE, CURRENT AND ENERGY DISSIPATION OF STEPWISE ADIABATIC CHARGING OF A CAPACITOR USING A NONRESONANT INDUCTOR CURRENT｣	Journal of Circuits, Systems, and Computers, Volume 23, No. 3, January 2014, pp. 1450039-1-21. doi: 10.1142/S021812661450039X Shunji Nakata, Hiroshi Makino, Ryota Honda, Masayuki Miyama, and Yoshio Matsuda	2014.01
｢Increase in Read Noise Margin of Single-bit-line SRAM using Adiabatic Change of Word Line Voltage｣	IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume 22, Issue 3, March 2014, pp.686-690. doi: 10.1109/TVLSI.2013.2247642 Shunji Nakata, Hiroki Hanazono, Hiroshi Makino, Hiroki Morimura, Masayuki Miyama, and Yoshio Matsuda	2014.03
｢Energy Efficient Stepwise Charging of a Capacitor Using a DC-DC Converter With Consecutive Changes of its Duty Ratio｣	IEEE Transactions on Circuits and Systems-I:Regular Papers, Volume 61, Issue 7, July 2014, pp.2194-2203. Doi: 10.1109/TCSI.2013.2295895 Shunji Nakata, Hiroshi Makino, Junpei Hosokawa, Tsutomu Yoshimura, Shuhei Iwade, and Yoshio Matsuda	2014.07
｢A Field Programmable Sequencer and Memory with Middle Grained Programmability Optimized for MCU Peripherals｣	IEICE Transactions on FUNDAMENTALS Vol.E99-A, No.5,May. 2016, pp. 917-928. Doi:10.1587/transfun.E99.A.917 Yoshifumi KAWAMURA, Naoya OKADA, Yoshio MATSUDA, Tetsuya MATSUMURA, Hiroshi MAKINO, and Kazutami ARIMOTO	2016.05
｢A Ring Oscillator Based All-digital On-chip Vth Measurement Circuit and Its Demonstration on FPGA Board｣	大阪工業大学紀要理工編, 67 巻 1 号, pp. 13-21, 2022 年 9 月 1 日, ISSN: 2188-9007. Hiroshi MAKINO,	2022.09

主な社会的活動等

Best Paper Award (IEEE International Conference on Computer Design 1993)
Best Paper Award (IEEE International Conference on Microelectronic Test Structures 2007)
平成26年度第162回システムとLSIの設計技術研究会優秀論文賞
(「メモリをベースにした省電力MCU内蔵フィールドプログラマブルデバイス」)
First Submission Award (IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS 2014))
平成28年電気関係学会関西連合大会にて連合大会奨励賞
(｢ばらつきを考慮した論理回路の電圧最適化に関する検討」)
令和3年電子情報通信学会エレクトロニクスソサイエティ学生奨励賞(2021年電子情報通信学会
総合大会での発表に対する受賞
｢不良出現を加速させたモンテカルロシミュレーションによるSRAMの動作限界推定｣
令和3年電気関係学会関西連合大会にて連合大会奨励賞
(｢SRAMのモンテカルロシミュレーションにおける一次元縮退モデルの適用と妥当性の検証」)
令和5年電気関係学会関西連合大会にて連合大会奨励賞
(｢SRAMのデータ保持時の不良率予測における一次元縮退モデルの妥当性検証」)

講義など協力可能なテーマ

LSI設計
低消費電力設計
ディジタル回路
回路シミュレーション
コンピュータアーキテクチャ